1 ps8178b 11/09/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI3B16232 3.3v, synchronous 16-bit to 32-bit fet mux/demux busswitch product description pericom semiconductors pi3b series of logic circuits are produced using the company's advanced 0.35micron cmos technology. the PI3B16232 is a 3.3 volt, 16-bit to 32-bit synchronous switch. two select inputs (s0 and s1) control the data flow. a clock (clk) and a clock enable (clken) synchronize the device operation. when clken is high, the bus switch remains in the last clocked function. 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI3B16232 3.3v, synchronous 16-bit to 32-bit fet mux/demux busswitch product features ? near-zero propagation delay. ?5 w switches connect between two ports ? packages available : - 56-pin 240mil wide thin plastic tssop(a) - 56-pin 300mil wide plastic ssop(v) product pin configuration logic block diagram truth table 1 s0 sk l cn e k l cn o i t c n u f xx x h e t a t s t s a l ll - lt c e n n o c s i d lh - l2 b = a d n a 1 b = a hl - l1 b = a hh - l2 b = a 56-pin a, v
2 ps8178b 11/09/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI3B16232 3.3v, synchronous 16-bit to 32-bit fet mux/demux busswitch dc electrical characteristics (over the operating range, t a = C40c to +85c, v cc = 3.0v to 3.6v) parameters description test conditions (1) min. typ (2) max. units v ih input high voltage guaranteed logic high level 2.0 v v il input low voltage guaranteed logic low level C0.5 0.8 v i ih input high current v cc = max., v in = v cc 1a i il input low current v cc = m ax . , v in = gnd 1 a i ozh high impedance output current 0 a, b v cc 1a v ik clamp diode voltage v cc = min.,v in = C18ma -0.7 -1.2 v ron switch on resistance (3) v cc = min., i in = 0.0v, i on = 48ma or 64ma 5 8 w v cc = min.,v in = 2.4 v, i on = 15ma 10 15 w capacitance (t a = 25c, f = 1 mhz) parameters (4) description test conditions typ. units c in input capacitance v in = 0v 3.0 pf c on a/b capacitance, switch on v in = 0v 25.0 pf storage temperature ..................................................... C65c to +150c ambient temperature with power applied .................... C40c to +85c supply voltage range ......................................................C0.5v to +4.6v dc input voltage .............................................................C0.5v to +4.6v dc output current ....................................................................... 120 ma power dissipation ............................................................................. 0.5w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device. 2. typical values are at vcc = 3.3v, t a = 25c ambient and maximum loading. 3. measured by the voltage drop between a and b pin at indicated current through the switch. on resistance is determined by the lower of the voltages on the two (a,b) pins. 4. this parameter is determined by device characterization but is not production tested. maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.)
3 ps8178b 11/09/98 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 PI3B16232 3.3v, synchronous 16-bit to 32-bit fet mux/demux busswitch power supply characteristics parameters description test conditions (1) min. typ (2) max. units i cc quiescent power v cc = m ax .v in = gnd or v cc 10a supply current d i cc supply current per v cc = m ax .v in = 3.0 v (3) 750 m a input @ ttl high i ccd supply current per v cc = max., 0.25 ma/ input per mhz (4) a and b pins open mhz be = gnd control input toggling 50% duty cycling notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for applicable device. 2. typical values are at vcc = 3.3v, +25c ambient. 3. per ttl driven input (control inputs only); a and b pins do not contribute to icc. 4. this current applies to the control inputs only and represent the current required to switch internal capacitance at the spec ified frequency. the a and b inputs generate no significant ac or dc currents as they transition. this parameter is not tested, but i s guaranteed by design. switching characteristics over operating range notes: 1. see test circuits and waveforms. 2. this parameter is guaranteed by design but not tested. 3. the bus switch contributes no propagational delay other than the rc delay of on resistance of the switch and the load capacitance. r e t e m a r a pn o i t p i r c s e ds n o i t i d n o c t s e t ) 1 ( v 6 . 3 o t 0 . 3 = c c v s t i n u . n i m. x a m f clk y c n e u q e r f k c o l c00 5 1z h m t w n o i t a r u d e s l u pw o l r o h g i h k l c3 . 3 s n s te m i t p u t e s k l c e r o f e b 1 s , 0 s - 9 . 1 k l c e r o f e b n e k l c - 9 . 1 h te m i t d l o h k l c r e t f a 1 s , 0 s - 1 k l c r e t f a n e k l c - 8 . 1 n e te m i t e l b a n e2 b , 1 b o t k l c15 s i d te m i t e l b a s i d2 b , 1 b o t k l c16 d p t 1 ) 3 , 2 ( n o i t a g a p o r p y a l e d b o t a5 2 . 0 d p t 2 n o i t a g a p o r p y a l e d a o t k l c15 . 4
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